By Harry D. Foster, Adam C. Krolnik, David J. Lacey
There is far pleasure within the layout and verification group approximately assertion-based layout. The query is, who may still examine assertion-based layout? The emphatic resolution is, either layout and verification engineers. What should be unintuitive to many layout engineers is that including assertions to RTL code will truly decrease layout time, whereas larger documenting layout purpose. each layout engineer should still learn this ebook! layout engineers that upload assertions to their layout won't merely decrease the time had to entire a layout, they're going to additionally decrease the variety of interruptions from verification engineers to reply to questions about layout motive and to handle verification suite blunders. With layout assertions in position, the vast majority of the interruptions from verification engineers can be on the topic of real layout difficulties and the mistake suggestions supplied can be extra precious to assist establish layout flaws. A layout engineer who doesn't upload assertions to the RTL code will spend extra time with verification engineers explaining the layout performance and meant interface requisites, wisdom that's wanted via the verification engineer to accomplish the activity of trying out the design.
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Additional info for Assertion-Based Design
3 phases of RTL implementation functional verification Many people consider the functional verification of an RTL implementation to be a process with a single goal: identify (and fix) bugs in the implementation. However, the functional verification process must actually ensure three distinct goals: 1 All lower-level RTL implementation details (outside the requirements established during specification and architect/ design) are bug-free 2 The RTL implementation satisfies all detailed requirements developed during the architect/design phase (which are outside the higher-level specification) 3 The RTL implementation satisfies all properties of its higher-level specification Meeting these goals is typically performed concurrently during the verification process, although they could be performed in a serial fashion.
For instance, it is important for all members of the design team to adopt the assertion methodology to give good assertion density across the entire design. If some members of the team don't believe that using assertion is worth their time, they are not inclined to add them. Likewise, if management agrees with the importance of the assertion methodology, they will encourage all of their employees to utilize assertions. If they believe it just adds to the overall schedule, they will either not encourage the use of assertions or actually discourage their use.
However, for any additional logic created to support the assertion that feeds into an assertion (for example, satellite FSMs to capture a special event), it is best to bracket this logic with an \ ifdef construct. Example 2-1 shows an example of this concept in Verilog. Compilation control of assertions 'ifdef ASSERT ON FIFO check: assert @(posedge elk) 'endif (reset_n => FIFO_depth < 7); If you use an assertion library, these commands should be placed within the library to reduce the designer's workload.